Reliability challenges for 45nm and beyond
Proceedings of the 43rd annual Design Automation Conference
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Process variation and temperature-aware reliability management
Proceedings of the Conference on Design, Automation and Test in Europe
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Representative critical reliability paths for low-cost and accurate on-chip aging evaluation
Proceedings of the International Conference on Computer-Aided Design
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Aging of transistors has become a major reliability concern especially when the VLSI circuits are in the nanometer regime. In this paper, we propose a novel methodology to address circuit aging in the field. On-chip aging sensor is designed to monitor transitions on functional paths capturing functional mode workload. Path delay is then accurately measured and converted to a digital value. Diagnosis and calibration are performed in the field, thereby achieving power-performance optimization throughout the entire lifetime. Simulation results demonstrate the efficiency of the proposed structure.