Roving Emulation as a Fault Detection Mechanism
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Low power integrated scan-retention mechanism
Proceedings of the 2002 international symposium on Low power electronics and design
Online BIST for Embedded Systems
IEEE Design & Test
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications
EDCC-2 Proceedings of the Second European Dependable Computing Conference on Dependable Computing
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Production Experience with Built-In Self-Test in the IBM ES/9000 System
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Versatile BIST: an integrated approach to on-line/off-line BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An analysis of power reduction techniques in scan testing
Proceedings of the IEEE International Test Conference 2001
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
Proceedings of the IEEE International Test Conference 2001
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
Effective Software Self-Test Methodology for Processor Cores
Proceedings of the conference on Design, automation and test in Europe
Testing of Hard Faults in Simultaneous Multithreaded Processors
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
NonStop® Advanced Architecture
DSN '05 Proceedings of the 2005 International Conference on Dependable Systems and Networks
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Survey of Test Vector Compression Techniques
IEEE Design & Test
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Verification Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective software-based self-test strategies for on-line periodic testing of embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Globally optimized robust systems to overcome scaled CMOS reliability challenges
Proceedings of the conference on Design, automation and test in Europe
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Operating system scheduling for efficient online self-test in robust systems
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer resilience challenges: metrics and optimization
Proceedings of the Conference on Design, Automation and Test in Europe
A self-adaptive system architecture to address transistor aging
Proceedings of the Conference on Design, Automation and Test in Europe
Run-time adaptive performance compensation using on-chip sensors
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Sampling + DMR: practical and low-overhead permanent fault detection
Proceedings of the 38th annual international symposium on Computer architecture
In-field aging measurement and calibration for power-performance optimization
Proceedings of the 48th Design Automation Conference
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
Application-aware diagnosis of runtime hardware faults
Proceedings of the International Conference on Computer-Aided Design
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Representative critical reliability paths for low-cost and accurate on-chip aging evaluation
Proceedings of the International Conference on Computer-Aided Design
A novel intermittent fault Markov model for deep sub-micron processors
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
On effective and efficient in-field TSV repair for stacked 3D ICs
Proceedings of the 50th Annual Design Automation Conference
A failure prediction strategy for transistor aging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Use it or lose it: wear-out and lifetime in future chip multiprocessors
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Memory block based scan-BIST architecture for application-dependent FPGA testing
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Stochastic error rate estimation for adaptive speed control with field delay testing
Proceedings of the International Conference on Computer-Aided Design
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CASP, Concurrent Autonomous chip self-test using Stored test Patterns, is a special kind of self-test where a system tests itself concurrently during normal operation without any downtime visible to the end-user. CASP consists of two ideas: 1. Storage of very thorough test patterns in non-volatile memory; and, 2. Architectural and system-level support for autonomous testing of one or more cores in a multi-core system using stored patterns, concurrently with normal system operation, without bringing down the entire system. CASP enables design of robust systems with built-in features for circuit failure prediction, error detection, self-diagnosis and self-repair. Such systems are necessary to overcome major reliability challenges in scaled-CMOS technologies. Implementation of CASP in the OpenSPARC T1 multi-core processor demonstrates its effectiveness and practicality.