Roving Emulation as a Fault Detection Mechanism
IEEE Transactions on Computers
ED4I: Error Detection by Diverse Data and Duplicated Instructions
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Detailed design and evaluation of redundant multithreading alternatives
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Dependable Computing and Online Testing in Adaptive and Configurable Systems
IEEE Design & Test
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Commercial Fault Tolerance: A Tale of Two Systems
IEEE Transactions on Dependable and Secure Computing
Trends in manufacturing test methods and their implications
ITC '04 Proceedings of the International Test Conference on International Test Conference
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Design for Resilience to Soft Errors and Variations
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
Gate-Oxide Early Life Failure Prediction
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware
SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer resilience challenges: metrics and optimization
Proceedings of the Conference on Design, Automation and Test in Europe
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Future system design methodologies must accept the fact that the underlying hardware will be imperfect, and enable design of robust systems that are resilient to hardware imperfections. Three techniques that can enable a sea change in robust system design are: 1. Built-In Soft Error Resilience (BISER), 2. Circuit Failure Prediction, and 3. Concurrent Autonomous self-test using Stored Patterns (CASP). Global optimization across multiple abstraction layers is essential for cost-effective robust system design using these techniques.