Globally optimized robust systems to overcome scaled CMOS reliability challenges
Proceedings of the conference on Design, automation and test in Europe
Operating system scheduling for efficient online self-test in robust systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Reliable cache design with detection of gate oxide breakdown using BIST
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Delay sensing for long-term variations and defects monitoring in safety---critical applications
Analog Integrated Circuits and Signal Processing
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
A failure prediction strategy for transistor aging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and on-chip monitoring of gate oxide breakdown in SRAM cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper uses 90nm transistor-level experimental data, device modeling, and circuit simulations to establish the following results: 1. A transistor with defective gateoxide,i.e., a gate-oxide early-life failure (ELF) candidate transistor, produces gradually degraded drive currents over time before it completely loses its transistor characteristics; 2. The above phenomenon results ingradual increase in delays of digital circuit paths containing the ELF candidate transistor before the circuit produces functional failures; 3. Gradual delay shifts caused by ELF candidate transistors are large enough to be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through ELF identification during production test or on-line during system operation.