A failure prediction strategy for transistor aging

Authors:
Hyunbean Yi;Tomokazu Yoneda;Michiko Inoue;Yasuo Sato;Seiji Kajihara;Hideo Fujiwara
Affiliations:
Department of Computer Engineering and Graduate School of Information and Communications, Hanbat National University, Daejeon, South Korea and Japan Science and Technology Agency, CREST, Tokyo, Ja ...;Graduate School of Information Science, Nara Institute of Science and Technology, Nara, Japan and Japan Science and Technology Agency, CREST, Tokyo, Japan;Graduate School of Information Science, Nara Institute of Science and Technology, Nara, Japan and Japan Science and Technology Agency, CREST, Tokyo, Japan;School of Computer Science and Systems Engineering, Kyusyu Institute of Technology, Iizuka, Japan and Japan Science and Technology Agency, CREST, Tokyo, Japan;School of Computer Science and Systems Engineering, Kyusyu Institute of Technology, Iizuka, Japan and Japan Science and Technology Agency, CREST, Tokyo, Japan;Faculty of Informatics, Osaka Gakuin University, Osaka, Japan and Japan Science and Technology Agency, CREST, Tokyo, Japan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircrafts, or medical equipments would not allow any interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure prediction technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms and the testing environment of voltage and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement technique considering the variation due to voltage and temperature and 2) an adaptive test scheduling that gives more test chances to more probable degrading parts. Experimental results show the required memory space and area cost for implementing the proposed technique.