Operating system scheduling for efficient online self-test in robust systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
A novel statistical and circuit-based technique for counterfeit detection in existing ICs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
The undetectable and unprovable hardware trojan horse
Proceedings of the 50th Annual Design Automation Conference
A failure prediction strategy for transistor aging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion
Journal of Electronic Testing: Theory and Applications
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Transistor aging results in circuit delay degradation over time,and is a growing concern for future systems. On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing.Effective circuit failure prediction requires very thorough testing to estimate the amount of aging in various parts of a large design during system operation. This paper introduces such testing techniques. Results on large designs demonstrate the practicality and effectiveness of presented techniques.