Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors
Proceedings of the 38th annual Design Automation Conference
Dynamic power management in a mobile multimedia system with guaranteed quality-of-service
Proceedings of the 38th annual Design Automation Conference
Power-aware scheduling under timing constraints for mission-critical embedded systems
Proceedings of the 38th annual Design Automation Conference
Thread-level parallelism and interactive performance of desktop applications
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
ETM10 Incorporates Hardware Segment of IEEE P1500
IEEE Design & Test
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BIST RESEEDING WITH VERY FEW SEEDS
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Low Overhead Test Point Insertion For Scan-Based BIST
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Energy-aware deterministic fault tolerance in distributed real-time embedded systems
Proceedings of the 41st annual Design Automation Conference
System-level energy-efficient dynamic task scheduling
Proceedings of the 42nd annual Design Automation Conference
Optimal procrastinating voltage scheduling for hard real-time systems
Proceedings of the 42nd annual Design Automation Conference
The Impact of Performance Asymmetry in Emerging Multicore Architectures
Proceedings of the 32nd annual international symposium on Computer Architecture
Hardware Ef.cient LBISTWith Complementary Weights
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
EFFICIENT PATTERN MAPPING FOR DETERMINISTIC LOGIC BIST
ITC '04 Proceedings of the International Test Conference on International Test Conference
BIST for Network-on-Chip Interconnect Infrastructures
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
The Impact of Multiple Failure Modes on Estimating Product Field Reliability
IEEE Design & Test
Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
(WCS)Operating System Concepts 7th Edition Flex Format
(WCS)Operating System Concepts 7th Edition Flex Format
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Efficient operating system scheduling for performance-asymmetric multi-core architectures
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Feedback-controlled reliability-aware power management for real-time embedded systems
Proceedings of the 45th annual Design Automation Conference
Gate-Oxide Early Life Failure Prediction
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Review of Low Frame Rate Effects on Human Performance
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
Cross-layer resilience challenges: metrics and optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
A failure prediction strategy for transistor aging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Very thorough online self-test is essential for overcoming major reliability challenges such as early-life failures and transistor aging in advanced technologies. This paper demonstrates the need for operating system (OS) support to efficiently orchestrate online self-test in future robust systems. Experimental data from an actual dual quad-core system demonstrate that, without software support, online self-test can significantly degrade performance of soft real-time and computation-intensive applications (by up to 190%), and can result in perceptible delays for interactive applications. To mitigate these problems, we develop OS scheduling techniques that are aware of online self-test, and schedule/migrate tasks in multi-core systems by taking into account the unavailability of one or more cores undergoing online self-test. These techniques eliminate any performance degradation and perceptible delays in soft real-time and interactive applications (otherwise introduced by online self-test), and significantly reduce the impact of online self-test on the performance of computation-intensive applications. Our techniques require minor modifications to existing OS schedulers, thereby enabling practical and efficient online self-test in real systems.