BIST for Network-on-Chip Interconnect Infrastructures

Authors:
Cristian Grecu;Partha Pande;Andre Ivanov;Res Saleh
Affiliations:
University of British Columbia, Canada;Washington State University;University of British Columbia, Canada;University of British Columbia, Canada
Venue:
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Year:
2006

Citing 0
Cited 13

Using the inter- and intra-switch regularity in NoC switch testing

Proceedings of the conference on Design, automation and test in Europe
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints

IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Diagnosis of interconnect shorts in mesh NoCs

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Operating system scheduling for efficient online self-test in robust systems

Proceedings of the 2009 International Conference on Computer-Aided Design
Improving the yield of NoC-based systems through fault diagnosis and adaptive routing

Journal of Parallel and Distributed Computing
Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers

Journal of Electronic Testing: Theory and Applications
ROBUST: a new self-healing fault-tolerant NoC router

Proceedings of the 4th International Workshop on Network on Chip Architectures
Structural Test and Diagnosis for Graceful Degradation of NoC Switches

Journal of Electronic Testing: Theory and Applications
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC

Microelectronics Journal
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Journal of Systems Architecture: the EUROMICRO Journal
Online traffic-aware fault detection for networks-on-chip

Journal of Parallel and Distributed Computing

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Abstract

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...