Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BIST for Network-on-Chip Interconnect Infrastructures
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
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The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip's primary inputs and outputs for controllability and observability. This is typically achieved by providing a dedicated Test Access Mechanism (TAM) between the wrapper and the primary inputs and outputs. However, when reusing the embedded Network-on-Chip (NoC) interconnect instead of the dedicated TAM, the standard wrapper cannot be used as is because of the packet-based transfer mechanism and other functional requirements by the NoC. In this paper, we describe two NoC-compatible wrappers, which overcome these limitations of the 1500 wrapper. The wrappers (Type 1 and Type 2) complement each other to optimize NoC bandwidth utilization while minimizing the area overhead. The Type 2 wrapper uses larger area overhead to increase bandwidth efficiency, while Type 1 takes advantage of some special configurations which may not require a complex and high-cost wrapper. Two wrapper optimization algorithms are applied to both wrapper designs under channel-bandwidth and test-time constraints, resulting in very little or no increase in the test application time compared to conventional dedicated TAM approaches.