Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
Robust, High-Speed Network Design for Large-Scale Multiprocessing
Robust, High-Speed Network Design for Large-Scale Multiprocessing
Tailoring router architectures to performance requirements in cut-through networks
Tailoring router architectures to performance requirements in cut-through networks
Computer Networks
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guaranteeing the quality of services in networks on chip
Networks on chip
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Quality-of-service and error control techniques for network-on-chip architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the 41st annual Design Automation Conference
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Debugging HW/SW interface for MPSoC: video encoder system design case study
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
An Application-Specific Design Methodology for STbus Crossbar Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Run-time support for heterogeneous multitasking on reconfigurable SoCs
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Feasibility analysis of messages for on-chip networks using wormhole routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bounded arbitration algorithm for QoS-supported on-chip communication
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A Study of NoC Exit Strategies
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Fast, Accurate and Detailed NoC Simulations
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
NoC design flow for TDMA and QoS management in a GALS context
EURASIP Journal on Embedded Systems
Power and reliability management of SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Run-time adaptive on-chip communication scheme
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
DNCOCO'07 Proceedings of the 9th WSEAS International Conference on Data Networks, Communications, Computers
Designing efficient irregular networks for heterogeneous systems-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
QoS-supported on-chip communication for multi-processors
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs
Microprocessors & Microsystems
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
IEICE - Transactions on Information and Systems
Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Custom networks-on-chip architectures with multicast routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Router designs for elastic buffer on-chip networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
Application-aware prioritization mechanisms for on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A routing algorithm for random error tolerance in network-on-chip
HCI'07 Proceedings of the 12th international conference on Human-computer interaction: applications and services
Communication modeling of multicast in all-port wormhole-routed NoCs
Journal of Systems and Software
Aérgia: exploiting packet latency slack in on-chip networks
Proceedings of the 37th annual international symposium on Computer architecture
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
Feedback control for providing QoS in NoC based multicores
Proceedings of the Conference on Design, Automation and Test in Europe
Configurable links for runtime adaptive on-chip communication
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive and deadlock-free tree-based multicast routing for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An analytical model of broadcast in QoS-aware wormhole-routed NoCs
Journal of Systems and Software
A generic adaptive path-based routing method for MPSoCs
Journal of Systems Architecture: the EUROMICRO Journal
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Power-efficient tree-based multicast support for networks-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Efficient switches for network-on-chip based embedded systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Topology-Aware quality-of-service support in highly integrated chip multiprocessors
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
RAPA: reliability-aware priority arbitration strategy for network on chip
Proceedings of the great lakes symposium on VLSI
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
A single-cycle output buffered router with layered switching for Networks-on-Chips
Computers and Electrical Engineering
Performance analysis and comparison of 2×4 network on chip topology
Microprocessors & Microsystems
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect
Fundamenta Informaticae - Application of Concurrency to System Design
An automatic design flow for mapping application onto a 2D mesh NoC architecture
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Hi-index | 0.00 |
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used. In this paper we show that guaranteed services are essential in achieving this decoupling. Guarantees typically come at the cost of lower resource utilization. To avoid this, they must be used in combination with best-effort services. The key element of our NoC is a router consisting conceptually of two parts: the so-called guaranteed throughput (GT) and best-effort (BE) routers. We combine the GT and BE router architectures in an efficient implementation by sharing resources. We show the trade offs between hardware complexity and efficiency of the combined router, and motivate our choices. Our reasoning for the trade offs is validated with a prototype router implementation. We show a lay-out of an input-queued wormhole 5 脳 5 router with an aggregate bandwidth of 80 Gbit/s. It occupies 0.26 mm2 in CMOS12. This shows that our router provides high performance at reasonable cost, bringing NoCs one step closer.