Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Issues in the development of a practical NoC: the Proteo concept
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A systematic approach to design low-power video codec cores
EURASIP Journal on Embedded Systems
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Algorithmic and architectural co-design of a motion-estimation engine for low-power video devices
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
SOC'09 Proceedings of the 11th international conference on System-on-chip
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
ACM Transactions on Embedded Computing Systems (TECS)
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In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.