Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Journal of Signal Processing Systems
Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration
Proceedings of the 45th annual Design Automation Conference
Journal of Signal Processing Systems
Placement of thermal vias in 3-D ICs using various thermal objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper introduces new design methodology and the corresponding EDA tool chain enabling fast design space exploration and high fidelity of results for emerging heterogeneous 3D-Stacked Integrated Circuits. The proposed framework allows designers to easily trade-off between different system level design choices (e.g. functional partitioning), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes) and understand their impact on typical design parameters such as cost, performance and power. We demonstrate the proposed framework using existing MPSoC for video coding applications. The system is virtually prototyped as traditional 2D and then 3D design. For a 3D version we place the off-chip DRAM memory on the top of the processing die, and consider different packaging options. For different implementation scenarios we quantify typical design parameters showing the benefits of the 3D integration.