Register allocation for software pipelined loops
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
LISA—machine description language for cycle-accurate models of programmable DSP architectures
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Computers
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Conversion of control dependence to data dependence
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Specifying and Compiling Applications for RaPiD
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Design and Tool Flow of Multimedia MPSoC Platforms
Journal of Signal Processing Systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design
Journal of Signal Processing Systems
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical very long instruction word-based digital signal processor, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors.