Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
A data locality optimizing algorithm
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Advanced compiler design and implementation
Advanced compiler design and implementation
Constraint-based array dependence analysis
ACM Transactions on Programming Languages and Systems (TOPLAS)
Parallel programming in OpenMP
Parallel programming in OpenMP
Compiler-directed scratch pad memory hierarchy design and management
Proceedings of the 39th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Analysis of Dynamic Structures for Efficient Parallel Execution
Proceedings of the 6th International Workshop on Languages and Compilers for Parallel Computing
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
Probabilistic source-level optimisation of embedded programs
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
An integrated scratch-pad allocator for affine and non-affine code
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic allocation for scratch-pad memory using compile-time decisions
ACM Transactions on Embedded Computing Systems (TECS)
HiveFlex-Video VSP1: Video Signal Processing Architecture for Video Coding and Post-Processing
ISM '06 Proceedings of the Eighth IEEE International Symposium on Multimedia
Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
The Impact of Higher Communication Layers on NoC Supported MP-SoCs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
SPRINT: a tool to generate concurrent transaction-level models from sequential code
EURASIP Journal on Applied Signal Processing
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Journal of Signal Processing Systems
An automatic scratch pad memory management tool and MPEG-4 encoder case study
Proceedings of the 45th annual Design Automation Conference
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
IEEE Transactions on Circuits and Systems for Video Technology
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This paper surveys components that are useful to build programmable, predictable, composable, and scalable multiprocessor-system-on-a-chip (MPSoC) multimedia platforms that can deliver high performance at high power-efficiency. A design-time tool flow is proposed to exploit all forms of parallelism on such platforms. As a first proof of concept, the flow is used to parallelize a relatively simple video standard on a platform consisting of off-the-shelf components. As a second proof of concept, we present the design of a high-performance platform with state-of-the-art components. This platform targets real-time H.264 high-definition video encoding at an estimated power consumption of 700 mW.