A 242mW, 10mm21080p H.264/AVC high profile encoder chip
Proceedings of the 45th annual Design Automation Conference
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Content-Aware Fast Motion Estimation for H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A low cost hardware oriented motion estimation algorithm for HDTV
Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation
Design and Tool Flow of Multimedia MPSoC Platforms
Journal of Signal Processing Systems
Selective search area reuse algorithm for low external memory access motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Motion estimation optimization for H.264/AVC using source image edge features
IEEE Transactions on Circuits and Systems for Video Technology
Low-power H.264 video compression architectures for mobile communication
IEEE Transactions on Circuits and Systems for Video Technology
A novel fast DCT coefficient scan architecture
PCS'09 Proceedings of the 27th conference on Picture Coding Symposium
PCS'09 Proceedings of the 27th conference on Picture Coding Symposium
Content aware configurable architecture for H.264/AVC integer motion estimation engine
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Real-time H.264 encoder implementation on a low-power digital signal processor
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Hardware design of motion data decoding process for H.264/AVC
Image Communication
PCM'07 Proceedings of the multimedia 8th Pacific Rim conference on Advances in multimedia information processing
Customizing wide-SIMD architectures for H.264
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Understanding sources of inefficiency in general-purpose chips
Proceedings of the 37th annual international symposium on Computer architecture
Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-performance three-engine architecture for H.264/AVC fractional motion estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
A case for multi-channel memories in video recording
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast mode decision based on RDO for AVS high definition video encoder
PCM'10 Proceedings of the Advances in multimedia information processing, and 11th Pacific Rim conference on Multimedia: Part II
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Journal of Signal Processing Systems
EURASIP Journal on Embedded Systems
Computers and Electrical Engineering
Understanding sources of ineffciency in general-purpose chips
Communications of the ACM
A scalable architecture for H.264/AVC variable block size motion estimation on FPGAs
WSEAS Transactions on Signal Processing
A real-time and parametric parallel video compression architecture using FPGA
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Journal of Signal Processing Systems
1080p 60 Hz Intra-Frame Video CODEC Chip Design and Its Implementation
Journal of Signal Processing Systems
Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC
Journal of Signal Processing Systems
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
Integration, the VLSI Journal
Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC
Journal of Signal Processing Systems
Convolution engine: balancing efficiency & flexibility in specialized computing
Proceedings of the 40th Annual International Symposium on Computer Architecture
Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System
Journal of Signal Processing Systems
An Adaptive Motion Estimation Architecture for H.264/AVC
Journal of Signal Processing Systems
Efficient smart-camera accelerator: A configurable motion estimator dedicated to video codec
Journal of Systems Architecture: the EUROMICRO Journal
An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding
Journal of Real-Time Image Processing
Fast Algorithm and Efficient Architecture for Integer and Fractional Motion Estimation
Journal of Signal Processing Systems
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H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency.