Techniques and standards for image, video, and audio coding
Techniques and standards for image, video, and audio coding
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
Journal of Signal Processing Systems
A configurable motion estimation architecture for block-matching algorithms
IEEE Transactions on Circuits and Systems for Video Technology
A 4-way pipelined processing architecture for three-step search block-matching motion estimation
IEEE Transactions on Consumer Electronics
An efficient VLSI architecture for H.264 variable block size motion estimation
IEEE Transactions on Consumer Electronics
IEEE Transactions on Consumer Electronics
Bit plane matching based variable block size motion estimation method and its hardware architecture
IEEE Transactions on Consumer Electronics
Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC
Journal of Signal Processing Systems
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A block-based gradient descent search algorithm for block motion estimation in video coding
IEEE Transactions on Circuits and Systems for Video Technology
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
IEEE Transactions on Circuits and Systems for Video Technology
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
An efficient architecture for motion estimation and compensation in the transform domain
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
IEEE Transactions on Circuits and Systems for Video Technology
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Parallel architectures for 3-step hierarchical search block-matching algorithm
IEEE Transactions on Circuits and Systems for Video Technology
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We introduce a variable block size motion estimation architecture that is adaptive to the full search (FS) and the three-step search (3SS) algorithms. Early termination, intensive data reuse, pipelined datapath with bit serial execution, and memory access management tailored to the search patterns of the FS and 3SS form key features of the architecture. The design was synthesized using Synopsys Design Compiler and 45nm standard cell library technology. The architecture sustains real-time CIF format with an operational frequency as low as 17.6MHz and consumes 1.98 mW at this clock rate. This architecture with its 500MHz peak operational frequency provides the end-user with the flexibility of choosing between video quality and throughput based on power consumption and processing speed constraints.