Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
Adaptive motion estimation processor for autonomous video devices
EURASIP Journal on Embedded Systems
Parallel motion estimation on the MDSP multiprocessor
Neural, Parallel & Scientific Computations
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Journal of Signal Processing Systems
Sub-block subsampling based block-matching motion estimation
AIC'04 Proceedings of the 4th WSEAS International Conference on Applied Informatics and Communications
A VLSI architecture for image registration in real time
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient hierarchical motion estimation algorithm and its VLSI architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Irregular Search Window Reuse Scheme for MPEG-2 to H.264 Transcoding
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Low Power Complexity-Reduced ME and Interpolation Algorithms for H.264/AVC
Journal of Signal Processing Systems
IEEE Transactions on Circuits and Systems for Video Technology
Selective search area reuse algorithm for low external memory access motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and design of a context adaptable SAD/MSE architecture
International Journal of Reconfigurable Computing
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
PCM'07 Proceedings of the multimedia 8th Pacific Rim conference on Advances in multimedia information processing
SoC Memory Hierarchy Derivation from Dataflow Graphs
Journal of Signal Processing Systems
Built-in self-detection/correction architecture for motion estimation computing arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computers and Electrical Engineering
An efficient memory hierarchy for full search motion estimation on high definition digital videos
Proceedings of the 24th symposium on Integrated circuits and systems design
An efficient VLSI architecture for full-search variable block size motion estimation in H.264/AVC
MMM'07 Proceedings of the 13th International conference on Multimedia Modeling - Volume Part II
ISVC'06 Proceedings of the Second international conference on Advances in Visual Computing - Volume Part II
Memory architecture evaluation for video encoding on enhanced embedded processors
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
An ontology infrastructure for multimedia reasoning
VLBV'05 Proceedings of the 9th international conference on Visual Content Processing and Representation
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Adaptive Motion Estimation Architecture for H.264/AVC
Journal of Signal Processing Systems
AMBER: adaptive energy management for on-chip hybrid video memories
Proceedings of the International Conference on Computer-Aided Design
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This work explores the data reuse properties of full-search block-matching (FSBM) for motion estimation (ME) and associated architecture designs, as well as memory bandwidth requirements. Memory bandwidth in high-quality video is a major bottleneck to designing an implementable architecture because of large frame size and search range. First, the memory bandwidth in ME is analyzed and the problem is solved by exploring data reuse. Four levels are defined according to the degree of data reuse for previous frame access. With the highest level of data reuse, one-access for frame pixels is achieved. A scheduling strategy is also applied to data reuse of the ME architecture designs and a seven-type classification system is developed that can accommodate most published ME architectures. This classification can simplify the work of designers in designing more cost-effective ME architectures, while simultaneously minimizing memory bandwidth. Finally, a FSBM architecture suitable for high quality HDTV video with a minimum memory bandwidth feature is proposed. Our architecture is able to achieve 100% hardware efficiency while preserving minimum I/O pin count, low local memory size, and bandwidth