Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
The MPEG-4 Book
A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Application Specific Instruction Set Processor for Adaptive Video Motion Estimation
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Low power distance measurement unit for real-time hardware motion estimators
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
IEEE Transactions on Circuits and Systems for Video Technology
A fast adaptive motion estimation algorithm
IEEE Transactions on Circuits and Systems for Video Technology
A configurable motion estimation architecture for block-matching algorithms
IEEE Transactions on Circuits and Systems for Video Technology
Fast motion estimation using configurable and extendible processing cores
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
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Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. As a consequence, with the proliferation of autonomous and portable handheld devices that support digital video coding, data-adaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an application-specific instruction set processor (ASIP) to implement data-adaptive motion estimation algorithms that is characterized by a specialized datapath and a minimum and optimized instruction set. Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices. Based on the proposed architecture and the considered adaptive algorithms, several motion estimators were synthesized both for a Virtex-II Pro XC2VP30 FPGA from Xilinx, integrated within an ML310 development platform, and using a StdCell library based on a 0.18 µm CMOS process. Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption. Moreover, it is also able to adapt the operation to the available energy level in runtime. By adjusting the search pattern and setting up a more convenient operating frequency, it can change the power consumption in the interval between 1.6mW and 15 mW.