Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Memory Architecture and Parallel Access
Memory Architecture and Parallel Access
Design Challenges of Technology Scaling
IEEE Micro
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
Adaptive motion estimation processor for autonomous video devices
EURASIP Journal on Embedded Systems
IEEE Transactions on Consumer Electronics
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
A multilevel successive elimination algorithm for block matching motion estimation
IEEE Transactions on Image Processing
Successive elimination algorithm for motion estimation
IEEE Transactions on Image Processing
A flexible parallel architecture adapted to block-matching motion-estimation algorithms
IEEE Transactions on Circuits and Systems for Video Technology
A block-based gradient descent search algorithm for block motion estimation in video coding
IEEE Transactions on Circuits and Systems for Video Technology
A novel unrestricted center-biased diamond search algorithm for block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Highly efficient predictive zonal algorithms for fast block-matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A novel cross-diamond search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Global elimination algorithm and architecture design for fast block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation
IEEE Transactions on Circuits and Systems for Video Technology
A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms
IEEE Transactions on Circuits and Systems for Video Technology
An efficient ME architecture for high definition videos using the new MPDS algorithm
Proceedings of the 24th symposium on Integrated circuits and systems design
International Journal of Reconfigurable Computing
An Adaptive Motion Estimation Architecture for H.264/AVC
Journal of Signal Processing Systems
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This paper introduces a configurable motion estimation architecture for a wide range of fast block-matching algorithms (BMAs). Contemporary motion estimation architectures are either too rigid for multiple BMAs or the flexibility in them is implemented at the cost of reduced performance. The proposed architecture overcomes both of these limitations. The configurability of the proposed architecture is based on a new BMA framework that can be adjusted to support the desired set of BMAs. The chosen framework configuration is implemented by an intelligent control logic which is integrated to an efficient parallel memory system and distortion computation unit. The flexibility of the framework is demonstrated by mapping five different BMAs (BBGDS, DS, CDS, HEXBS, and TSS) to the architecture. The total execution time of the mapped BMAs is shown to be almost directly proportional to the number of tested checking points in the search area, so the architecture is very tolerant of different BMA-specific search strategies and search patterns. In addition, a run-time switching between supported BMAs can be done without performance compromises. With a 0.13-µm CMOS technology, the proposed architecture configured for HEXBS, BBGDS, and TSS requires only 14.2 kgates and 2.5 KB of memory at 200 MHz operating frequency. A performance comparison to the reference programmable architectures reveals that only the proposed implementation is able to process real-time (30 fps) fixed block-size motion estimation (1 reference frame) at full HDTV resolution (1920 × 1080).