Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
A configurable motion estimation architecture for block-matching algorithms
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient VLSI architecture for H.264 variable block size motion estimation
IEEE Transactions on Consumer Electronics
An efficient hardware implementation for motion estimation of AVC standard
IEEE Transactions on Consumer Electronics
IEEE Transactions on Consumer Electronics
Architecture Design for H.264/AVC Integer Motion Estimation with Minimum Memory Bandwidth
IEEE Transactions on Consumer Electronics
A high-performance reconfigurable VLSI architecture for vbsme in H.264
IEEE Transactions on Consumer Electronics
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
IEEE Transactions on Circuits and Systems for Video Technology
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
IEEE Transactions on Circuits and Systems for Video Technology
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation
IEEE Transactions on Circuits and Systems for Video Technology
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Parallel architectures for 3-step hierarchical search block-matching algorithm
IEEE Transactions on Circuits and Systems for Video Technology
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Motion estimation (ME) is the most critical component of a video coding standard. H.264/AVC adopts the variable block size motion estimation (VBSME) to obtain excellent coding efficiency, but the high computational complexity makes design difficult. This paper presents an effective processor chip for integer motion estimation (IME) in H264/AVC based on the full-search block-matching algorithm (FSBMA). It uses architecture with a configurable 2D systolic array to obtain a high data reuse of search area. This systolic array supports a three-direction scan format in which only one row of pixels is changed between the two adjacent subblocks, thus reducing the memory accesses and saving clock cycles. A computing array of 64 PEs calculates the SAD of basic 4x4 subblocks and a modified Lagrangian cost is used as matching criterion to find the best 41 variable-size blocks by means of a tree pipeline parallel architecture. Finally, a mode decision module uses serial data flow to find the best mode by comparing the total minimum Lagrangian costs. The IME processor chip was designed in UMC 0.18@mm technology resulting in a circuit with only 32.3k gates and 6 RAMs (total 59kBits on-chip memory). In typical working conditions (25^oC, 1.8V), a clock frequency of 300MHz can be estimated with a processing capacity for HDTV (1920x1088 @ 30fps) and a search range of 32x32.