An efficient hardware implementation for motion estimation of AVC standard

Authors:
Lei Deng;Wen Gao;Ming Zeng Hu;Zhen Zhou Ji
Affiliations:
Harbin Inst. of Technol., China;-;-;-
Venue:
IEEE Transactions on Consumer Electronics
Year:
2005

Citing 0
Cited 13

Testable design techniques for variable block size motion estimator used in H.264/AVC

AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding

Proceedings of the 13th international symposium on Low power electronics and design
High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Journal of Signal Processing Systems
enBudget: a run-time adaptive predictive energy-budgeting scheme for energy-aware motion estimation in H.264/MPEG-4 AVC video encoder

Proceedings of the Conference on Design, Automation and Test in Europe
Testable design techniques for variable block size motion estimator used in H.264/AVC

IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC

Image Communication
An efficient memory hierarchy for full search motion estimation on high definition digital videos

Proceedings of the 24th symposium on Integrated circuits and systems design
Algorithms and hardware architectures for variable block size motion estimation

UIC'11 Proceedings of the 8th international conference on Ubiquitous intelligence and computing
Adaptive search range scaling for b pictures coding

PCM'06 Proceedings of the 7th Pacific Rim conference on Advances in Multimedia Information Processing
Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation

Journal of Signal Processing Systems
A memory hierarchy model based on data reuse for full-search motion estimation on high-definition digital videos

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding

Journal of Real-Time Image Processing

Quantified Score

Hi-index	0.43

Visualization

Abstract

In the advanced video coding standard (AVC), motion estimation adopts many new features such as variable block size searching, multiple reference frames, motion vector prediction, etc, for enhancing the coding performance. However, the high data dependence and high computation requirement of these new features makes the hardware implementation very complex, especially for real-time applications. Therefore base on the reference software JM9.0, this paper firstly improved the motion estimation algorithm from hardware-oriented viewpoint, and secondly proposed the systolic architecture of improved algorithm. It adopts 2-D systolic arrays, fully supports the AVC 's variable block size matching, and can produce 41 motion vectors for one macroblock. Experimental results show that the improved algorithm can avoid the data dependences while with the same coding performance as JM9.0, and the proposed architecture can achieve the real-time requirement for 720×576 picture size at 30 fps with the search range of 65×65.