Performance enhancement of H.263 encoder based on zero coefficient prediction
MULTIMEDIA '97 Proceedings of the fifth ACM international conference on Multimedia
Computer
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Conversion of reference C code to dataflow model: H.264 encoder case study
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A near optimal deblocking filter for H.264 advanced video coding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
High throughput architecture for H.264/AVC forward transforms block
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
H.264 Implementation with Embedded Reconfigurable Architecture
CIT '06 Proceedings of the Sixth IEEE International Conference on Computer and Information Technology
Fast H.264/AVC Inter-Mode Decision with RDC Optimization
IIH-MSP '06 Proceedings of the 2006 International Conference on Intelligent Information Hiding and Multimedia
An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC
IEICE - Transactions on Information and Systems
A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC
MUE '07 Proceedings of the 2007 International Conference on Multimedia and Ubiquitous Engineering
Proceedings of the conference on Design, automation and test in Europe
A Self-Adaptive Extensible Embedded Processor
SASO '07 Proceedings of the First International Conference on Self-Adaptive and Self-Organizing Systems
RISPP: rotating instruction set processing platform
Proceedings of the 44th annual Design Automation Conference
Fine- and Coarse-Grain Reconfigurable Computing
Fine- and Coarse-Grain Reconfigurable Computing
Fast sub-pixel motion estimation techniques having lower computational complexity
IEEE Transactions on Consumer Electronics
An efficient VLSI architecture for H.264 variable block size motion estimation
IEEE Transactions on Consumer Electronics
An efficient hardware implementation for motion estimation of AVC standard
IEEE Transactions on Consumer Electronics
Computation reduction for motion search in low rate video coders
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Rate-constrained coder control and comparison of video coding standards
IEEE Transactions on Circuits and Systems for Video Technology
An effective variable block-size early termination algorithm for H.264 video coding
IEEE Transactions on Circuits and Systems for Video Technology
Optimum bit allocation and rate control for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
KAHRISMA: a novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Instruction scheduling for reliability-aware compilation
Proceedings of the 49th Annual Design Automation Conference
An efficient multi-core SIMD implementation for H.264/AVC encoder
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting program-level masking and error propagation for constrained reliability optimization
Proceedings of the 50th Annual Design Automation Conference
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Proceedings of the International Conference on Computer-Aided Design
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The H.264/AVC video coding standard features diverse computational hot spots that need to be accelerated to cope with the significantly increased complexity compared to previous standards. In this paper, we propose an optimized application structure (i.e. the arrangement of functional components of an application determining the data flow properties) for the H.264 encoder which is suitable for application-specific and reconfigurable hardware platforms. Our proposed application structural optimization for the computational reduction of the Motion Compensated Interpolation is independent of the actual hardware platform that is used for execution. For a MIPS processor we achieve an average speedup of approximately 60脳 for Motion Compensated Interpolation. Our proposed application structure reduces the overhead for Reconfigurable Platforms by distributing the actual hardware requirements amongst the functional blocks. This increases the amount of available reconfigurable hardware per Special Instruction (within a functional block) which leads to a 2.84脳 performance improvement of the complete encoder when compared to a Benchmark Application with standard optimizations. We evaluate our application structure by means of four different hardware platforms.