An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Architecture design for deblocking filter in H.264/JVT/AVC
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
An efficient architecture for adaptive deblocking filter of H.264/AVC video coding
IEEE Transactions on Consumer Electronics
A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC
IEEE Transactions on Consumer Electronics
Introduction to the special issue on the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Journal of Signal Processing Systems
A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter
Proceedings of the 21st annual symposium on Integrated circuits and system design
High performance architecture of an application specific processor for the H.264 deblocking filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Performance Optimized Architecture of Deblocking Filter in H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Programmable deblocking filter architecture for a VC-1 video decoder
IEEE Transactions on Circuits and Systems for Video Technology
A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Journal of Signal Processing Systems
A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration
Journal of Signal Processing Systems
A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process
Journal of Signal Processing Systems
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We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant saving in filtering time, local memory usage, and memory traffic. Every 16x16 macroblock requires 192 filtering operations. After a few initialization cycles, our 5-stage pipelined architecture is able to perform one filtering operation per cycle. Compared with some state-of-the-art designs, our architecture delivers the fastest level of performance while using much smaller gate count and memory. We have implemented and integrated the proposed deblocking filter into an H.264 main profile video decoder and verified it with an FPGA prototype.