A near optimal deblocking filter for H.264 advanced video coding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Highly Parallel Architecture for Deblocking Filter in H.264/AVC
IEICE - Transactions on Information and Systems
Subjective Multimedia Quality Assessment
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC
IEICE - Transactions on Information and Systems
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule
IEEE Transactions on Circuits and Systems for Video Technology
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The paper presents a new architecture for implementation of an H.264/MPEG-4 AVC deblocking filter in hardware. This architecture adopts an innovative 4-stage pipelined structure in the edge filter. The proposed approach redesigns internal filter datapaths and memory organization in order to reduce both global processing cycles per macroblock and chip area. A comparison with other previous related works indicated that the proposed architecture offers significant gains for practical implementation in embedded systems, which commonly have restrictions in power consumption, clock speed and memory capability.