A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter
Proceedings of the 21st annual symposium on Integrated circuits and system design
Configurable VLSI architecture for deblocking filter in H.264/AVC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register array structure for effective edge filtering operation of deblocking filter
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration
Journal of Signal Processing Systems
A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process
Journal of Signal Processing Systems
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This paper presents a highly parallel architecture for deblocking filter in H.264/AVC. We adopt various parallel schemes in memory sub-system and datapath. A 2-dimensional parallel memory scheme is employed to support efficient parallel access in both horizontal and vertical directions in order to speed up the whole filtering process. This parallel memory also eliminates the need for a transpose circuit. In the datapath, an algorithm optimization is performed to implement parallel filtering with hardware reuse. Pipeline techniques are also adopted to improve the throughput of filtering operations. Our design is implemented under TSMC 0.18 μm technology. Results show that the core size is 0.82 × 1.13 mm2 when the maximum frequency is 230 MHz. Compared to other existing architectures, our design has advantages in both speed and area.