A near optimal deblocking filter for H.264 advanced video coding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Highly Parallel Architecture for Deblocking Filter in H.264/AVC
IEICE - Transactions on Information and Systems
A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC
MUE '07 Proceedings of the 2007 International Conference on Multimedia and Ubiquitous Engineering
A pipelined hardware implementation of in-loop deblocking filter in H.264/AVC
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture which is designed with the minimum hardware cost compared to other kinds of architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.