Journal of Signal Processing Systems
A High Performance H.264 Deblocking Filter
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
High performance architecture of an application specific processor for the H.264 deblocking filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
Journal of Signal Processing Systems
A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration
Journal of Signal Processing Systems
A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process
Journal of Signal Processing Systems
A Very High Throughput Deblocking Filter for H.264/AVC
Journal of Signal Processing Systems
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In this paper we present a pipelined hardware implementation of in-loop deblocking filter in H.264/AVC. A pipelined datapath has been adopted to boost the speed of the deblocking filter process. The processing order of the filter is rearranged to facilitate the deblocking of the pixels in a pipelined fashion. A suitable buffer mechanism has also been proposed that reduces the size of the on-chip SRAM and redundant external memory accesses. The hardware implementation, under TSMC 0.13 μm standard cell library, consumes only 7.5 K gates at a clock frequency of 200 MHz. Our architecture supports real-time deblocking of high resolution (2048×1024) video applications at 30 fps over three channels.