Configurable VLSI architecture for deblocking filter in H.264/AVC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Efficient Architecture for Deblocking Filter in H.264/AVC
IIH-MSP '09 Proceedings of the 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing
A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A pipelined hardware implementation of in-loop deblocking filter in H.264/AVC
IEEE Transactions on Consumer Electronics
An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a dedicated data arrangement in local memory banks, the proposed architecture can process filtering operations for one macroblock with less filtering cycles than previously proposed approaches. Whereas, filtering efficiency is improved due to a novel computation scheduling and a dedicated architecture composed of six filtering cores. It can be used either into the decoder or the encoder as a hardware accelerator for the processor or can be embedded into a full-hardware codec. This developed Intellectual Property block-based on the proposed architecture supports multiple and high definition processing flows in real time. While working at clock frequency of 150 MHz, synthesized under 65 nm low power and low voltage CMOS standard cell technology, it easily meets the throughput requirements for 4 k video at 30 fps of all the levels in H.264/AVC video coding standard and consumes 25.08 Kgates.