High performance architecture of an application specific processor for the H.264 deblocking filter

Authors:
Philip Dang
Affiliations:
STMicroelectronics, Inc., La Jolla, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 13
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Abstract

This paper presents an efficient architecture of an application specific processor (ASP) designed for the deblocking filter algorithm of the H.264 video compression standard. Several optimization techniques at different design levels, such as vector register, pipeline processing, very long instruction word (VLIW) processor, and predication, are utilized in this design. The proposed ASP can meet the real time constraint of the deblocking filter algorithm for the 16:9 video format (4690 × 2304) at 30 frames per second (fps) at 200-MHz clock rate.