A near optimal deblocking filter for H.264 advanced video coding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast Blind Measurement of Blocking Artifacts in both Pixel and DCT Domains
Journal of Mathematical Imaging and Vision
Journal of Signal Processing Systems
A High Performance H.264 Deblocking Filter
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
Configurable VLSI architecture for deblocking filter in H.264/AVC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance architecture of an application specific processor for the H.264 deblocking filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Performance Optimized Architecture of Deblocking Filter in H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
Journal of Signal Processing Systems
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
Journal of Signal Processing Systems
A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register array structure for effective edge filtering operation of deblocking filter
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
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This paper proposes an efficient hardware architecture to accelerate adaptive deblocking filter of H.264/A VC video coding. Compact data access unit, line-of-pixel (LOP) is defined in this paper. Line-of-pixel and build-in data buffer are employed to simplify data exchange between deblocking filter and outside data memory. Edge filter, which is designed to process each group of pixels on both sides of one edge, is kernel of deblocking filter. It is implemented in multiple parallel pipelines to increase efficiency. By carefully design, the proposed deblocking filter can be embedded in general-purpose processor or DSP to support special instructions for acceleration of software codec. This filter also can be used to full hardware H. 264/A VC codec.