Architecture design for deblocking filter in H.264/JVT/AVC
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
A Highly Parallel Architecture for Deblocking Filter in H.264/AVC
IEICE - Transactions on Information and Systems
An efficient architecture for adaptive deblocking filter of H.264/AVC video coding
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Hi-index | 0.00 |
In this paper we propose a novel deblocking filter architecture using register array structure for standard video codec hardware. The proposed register array consists of multiple sub-macroblocks for a single macroblock and several sub-macroblock registers for the up and left neighboring macroblocks. The operation procedure of the register array is also presented. The proposed register array achieves fast operating speed and small circuit size at the same time