A near optimal deblocking filter for H.264 advanced video coding
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
Journal of Signal Processing Systems
Configurable folded array for FIR filtering
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems
Configurable VLSI architecture for deblocking filter in H.264/AVC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance architecture of an application specific processor for the H.264 deblocking filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Performance Optimized Architecture of Deblocking Filter in H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
Journal of Signal Processing Systems
Low-power H.264 video compression architectures for mobile communication
IEEE Transactions on Circuits and Systems for Video Technology
A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Realization of deblocking filter in FPGA: based on the compression standard of H.264 coding
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
Journal of Signal Processing Systems
Performance improvement of H.264/AVC deblocking filter by using variable block sizes
ACIVS'07 Proceedings of the 9th international conference on Advanced concepts for intelligent vision systems
A two-result-per-cycle deblocking filter architecture for QFHD H.264/AVC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register array structure for effective edge filtering operation of deblocking filter
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Low-Power h.264 deblocking filter algorithm and its soc implementation
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
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This paper presents an efficient VLSI architecture for the deblocking filter in H.264/JVT/AVC. We use an array of 8/spl times/4 8-bit shift registers with reconfigurable data path to support both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Two SRAM modules are carefully organized not only for the storage of current macroblock data and adjacent block data but also for the efficient access of pixels in different blocks. Simulation results show that under 0.25 /spl mu/m technology, the synthesized logic gate count is only 19.1 K (not including a 96/spl times/32 SRAM and a 64/spl times/32 SRAM) when the maximum frequency is 100 MHz. Our architecture design can easily support real-time deblocking of 720p (1280/spl times/720) 30 Hz video. It is valuable for platform-based design of H.264 codec.