A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Architecture design for deblocking filter in H.264/JVT/AVC
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Low-power VLSI design for motion estimation using adaptive pixel truncation
IEEE Transactions on Circuits and Systems for Video Technology
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Rate-constrained coder control and comparison of video coding standards
IEEE Transactions on Circuits and Systems for Video Technology
Low-power H.264/AVC baseline decoder for portable applications
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization
Journal of Signal Processing Systems
Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A VLSI-oriented algorithm and its implementation for AVS chroma interpolation
Image Communication
A parallel motion estimation engine for H.264 encoding using the UMHexagonS algorithm
Proceedings of the 2009 International Conference on Hybrid Information Technology
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
Journal of Signal Processing Systems
Customizing wide-SIMD architectures for H.264
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
An H.264/SVC memory architecture supporting spatial and course-grained quality scalabilities
ICIP'09 Proceedings of the 16th IEEE international conference on Image processing
Journal of Signal Processing Systems
Low-power bitstream-residual decoder for H.264/AVC baseline profile decoding
EURASIP Journal on Embedded Systems
A 720p H.264/AVC decoder ASIC implementation for digital television set-top boxes
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
A dual quad-tree based variable block-size coding method
Journal of Visual Communication and Image Representation
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia
Proceedings of the International Conference on Computer-Aided Design
Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels--A Showcase
Journal of Signal Processing Systems
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
Integration, the VLSI Journal
Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System
Journal of Signal Processing Systems
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H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and memory access requirement make the hardwired codec solution a tough job. This paper describes the design methodology for H.264/AVC video codec. The system architecture and scheduling will be addressed. The design consideration and optimization for its significant modules including bandwidth optimized motion compensation engine, reconfigurable intra predictor generator, low bandwidth parallel integer motion estimation will be mentioned. Due to the complex, sequential, and highly data-depended characteristics of all essential algorithms in H.264/AVC, not only the pipeline structure but also efficient memory hierarchy is required. The design case with a hybrid task pipelining scheme, a balanced schedule with block-level, MB-level, and frame-level pipelining, will be presented. By combining with many bandwidth reduction techniques and data reused schemes, very efficient architecture and implementation for plate-form based system is proved by the prototype chips.