Partitioning and pipelining for performance-constrained hardware/software systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of heterogenous multi-processor embedded systems: applying functional pipelining
PACT '97 Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques
Multigrain Parallel Processing for JPEG Encoding on a Single Chip Multiprocessor
IWIA '02 Proceedings of the International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02)
Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Heterogeneous multiprocessor implementations for JPEG:: a case study
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A control theoretic approach to energy-efficient pipelined computation in MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Design methodology for pipelined heterogeneous multiprocessor system
Proceedings of the 44th annual Design Automation Conference
3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding
Proceedings of the 13th international symposium on Low power electronics and design
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A design flow for application specific heterogeneous pipelined multiprocessor systems
Proceedings of the 46th Annual Design Automation Conference
Power Management of Datacenter Workloads Using Per-Core Power Gating
IEEE Computer Architecture Letters
A feedback-based approach to DVFS in data-flow applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Macro pipelining based scheduling on high performance heterogeneousmultiprocessor systems
IEEE Transactions on Signal Processing
A 90-nm Low-Power FPGA for Battery-Powered Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the International Conference on Computer-Aided Design
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia
Proceedings of the International Conference on Computer-Aided Design
Adaptive power management of on-chip video memory for multiview video coding
Proceedings of the 49th Annual Design Automation Conference
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs
Proceedings of the 49th Annual Design Automation Conference
Energy optimization with worst-case deadline guarantee for pipelined multiprocessor systems
Proceedings of the Conference on Design, Automation and Test in Europe
EVA: an efficient vision architecture for mobile systems
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Agent-based distributed power management for kilo-core processors
Proceedings of the International Conference on Computer-Aided Design
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Pipelined MPSoCs provide a high throughput implementation platform for multimedia applications, with reduced design time and improved flexibility. Typically a pipelined MPSoC is balanced at design-time using worst-case parameters. Where there is a widely varying workload, such designs consume exorbitant amount of power. In this paper, we propose a novel adaptive pipelined MPSoC architecture that adapts itself to varying workloads. Our architecture consists of Main Processors and Auxiliary Processors with a distributed run-time balancing approach, where each Main Processor, independent of other Main Processors, decides for itself the number of required Auxiliary Processors at run-time depending on its varying workload. The proposed run-time balancing approach is based on off-line statistical information along with workload prediction and run-time monitoring of current and previous workloads' execution times. We exploited the adaptability of our architecture through a case study on an H.264 video encoder supporting HD720p at 30 fps, where clock- and power-gating were used to deactivate idle Auxiliary Processors during low workload periods. The results show that an adaptive pipelined MPSoC provides energy savings of up to 34% and 40% for clock- and power-gating based deactivation of Auxiliary Processors respectively with a minimum throughput of 29 fps when compared to a design-time balanced pipelined MPSoC.