Heterogeneous multiprocessor implementations for JPEG:: a case study

Authors:
Seng Lin Shee;Andrea Erdos;Sri Parameswaran
Affiliations:
The University of New South Wales, Sydney, NSW, Australia;The University of New South Wales, Sydney, NSW, Australia;The University of New South Wales, Sydney, NSW, Australia
Venue:
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Year:
2006

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Abstract

Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we explore the use of multiple cores to speed up the JPEG compression algorithm. We show two methods to parallelize this algorithm: one, a master-slave model; and two, a pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues. We show that even with this relatively simple application, parallelization can be carried out with up to nine processors with utilization of between 50% to 80%. We obtained speed ups of up to 4.6X with a seven core system with an area increase of 3.1X.