Analyzing Asynchronous Pipeline Schedules
International Journal of Parallel Programming
A Pipeline-Based Approach for Scheduling Video Processing Algorithms on NOW
IEEE Transactions on Parallel and Distributed Systems
Determining Asynchronous Acyclic Pipeline Execution Times
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Automatic Scheduler for Real-Time Vision Applications
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Heterogeneous multiprocessor implementations for JPEG:: a case study
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Design methodology for pipelined heterogeneous multiprocessor system
Proceedings of the 44th annual Design Automation Conference
Architectural exploration of heterogeneous multiprocessor systems for JPEG
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 11th Annual conference on Genetic and evolutionary computation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A design flow for application specific heterogeneous pipelined multiprocessor systems
Proceedings of the 46th Annual Design Automation Conference
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
Towards fully adaptive pipeline parallelism for heterogeneous distributed environments
ISPA'06 Proceedings of the 4th international conference on Parallel and Distributed Processing and Applications
MultiMaKe: Chip-multiprocessor driven memory-aware kernel pipelining
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A survey of pipelined workflow scheduling: Models and algorithms
ACM Computing Surveys (CSUR)
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Presents a technique for pipelining heterogeneous multiprocessor systems, macro pipelining based scheduling. The problem can be identified as a combination of optimal task/processor assignment to pipeline stages as well as a scheduling problem. The authors propose a new technique based on iterative applications of partitioning and scheduling schemes whereby the number of pipeline stages are identified and the scheduling problem is solved. The pipeline cycle is optimized in two steps. The first step finds a global coarse solution using the ratio cut partitioning technique. This is subsequently improved by the iterative architecture driven partitioning and the repartitioning and time axis relabeling techniques of the second step. The authors have considered a linear interprocessor communication cost model in scheduling. The proposed technique is applied to several examples. They find that for these examples, the proposed macro pipelining based scheduling can improve the throughput rate several times that of the conventional homogeneous multiprocessor scheduling algorithms