EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Partitioning and pipelining for performance-constrained hardware/software systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design & Test
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Design of heterogenous multi-processor embedded systems: applying functional pipelining
PACT '97 Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Multigrain Parallel Processing for JPEG Encoding on a Single Chip Multiprocessor
IWIA '02 Proceedings of the International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02)
Synthesis of Application Specific Multiprocessor Architectures for Process Networks
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
Proceedings of the 31st annual international symposium on Computer architecture
Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming
ICPADS '05 Proceedings of the 11th International Conference on Parallel and Distributed Systems - Workshops - Volume 02
4G applications, architectures, design methodology and tools for MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
Heterogeneous multiprocessor implementations for JPEG:: a case study
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Design methodology for pipelined heterogeneous multiprocessor system
Proceedings of the 44th annual Design Automation Conference
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A design flow for application specific heterogeneous pipelined multiprocessor systems
Proceedings of the 46th Annual Design Automation Conference
Rapid runtime estimation methods for pipelined MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Macro pipelining based scheduling on high performance heterogeneousmultiprocessor systems
IEEE Transactions on Signal Processing
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compositional system-level design exploration with planning of high-level synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Combining computation and communication optimizations in system synthesis for streaming applications
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Run-time adaption for highly-complex multi-core systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
| Hi-index | 0.00 |
A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specific Instruction set Processors (ASIPs), called a pipelined MPSoC. The latency and throughput requirements of streaming applications put constraints on the design of such a pipelined MPSoC, where each ASIP has a number of available configurations differing by additional instructions, and instruction and data cache sizes. Thus, the design space of a pipelined MPSoC is all the possible combinations of ASIP configurations (design points). In this paper, a methodology is proposed to optimize the area of a pipelined MPSoC under a latency or a throughput constraint. The final design point is a set of ASIP configurations with one configuration for each ASIP. We proposed an Integer Linear Programming (ILP) based solution to the area optimization problem under a latency constraint, and an algorithm for optimization of pipelined MPSoC area under a throughput constraint. The proposed solutions were evaluated using four streaming applications: JPEG encoder; JPEG decoder; MP3 encoder; and H.264 decoder. The time to find the Pareto front of each pipelined MPSoC was less than 4 minutes where design spaces had up to 1016 design points, illustrating the applicability of our approach.