Fine-grain design space exploration for a cartographic SoC multiprocessor
ACM SIGARCH Computer Architecture News
Synthesis of an application-specific soft multiprocessor system
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
MAPS: an integrated framework for MPSoC application parallelization
Proceedings of the 45th annual Design Automation Conference
Synthesis algorithm for application-specific homogeneous processor networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid runtime estimation methods for pipelined MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia
Proceedings of the International Conference on Computer-Aided Design
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Practice shows that increasing the amount of instruction level parallelism (ILP) offered by an architecture (like adding instruction slots to VLIW instructions) does not necessary lead to significant performance gains. Instead, high hardware costs and inefficient use of this hardware may occur. Mapping embedded applications onto multiprocessor systems forms a very interesting extension to ILP. The authors describe their approach to the mapping of embedded programs written in ANSI C onto a pipeline of application specific processors. An efficient algorithm for functional pipelining of loops is presented. To validate its applicability the frequency tracking system is used as a case study. This typical embedded application is mapped onto a two-processor system delivering speedup of 1.88 in comparison with a highly optimized single core solution.