A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Design of heterogenous multi-processor embedded systems: applying functional pipelining
PACT '97 Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques
Online strategies for dynamic power management in systems with multiple power-saving states
ACM Transactions on Embedded Computing Systems (TECS)
Balancing System Level Pipelines with Stage Voltage Scaling
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Heterogeneous multiprocessor implementations for JPEG:: a case study
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A control theoretic approach to energy-efficient pipelined computation in MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Design methodology for pipelined heterogeneous multiprocessor system
Proceedings of the 44th annual Design Automation Conference
Chameleon: Application-Level Power Management
IEEE Transactions on Mobile Computing
Thread motion: fine-grained power management for multi-core systems
Proceedings of the 36th annual international symposium on Computer architecture
Power Management of Datacenter Workloads Using Per-Core Power Gating
IEEE Computer Architecture Letters
A feedback-based approach to DVFS in data-flow applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Proceedings of the 48th Design Automation Conference
A 90-nm Low-Power FPGA for Battery-Powered Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive power management of on-chip video memory for multiview video coding
Proceedings of the 49th Annual Design Automation Conference
Accurate characterization of the variability in power consumption in modern mobile processors
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
Run-time adaption for highly-complex multi-core systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Agent-based distributed power management for kilo-core processors
Proceedings of the International Conference on Computer-Aided Design
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System-level dynamic power management (DPM) schemes in Multi-processor System on Chips (MPSoCs) exploit the idleness of processors to reduce the energy consumption by putting idle processors to low-power states. In the presence of multiple low-power states, the challenge is to predict the duration of the idle period with high accuracy so that the most beneficial power state can be selected for the idle processor. In this work, we propose a novel dynamic power management scheme for adaptive pipelined MPSoCs, suitable for multimedia applications. We leverage application knowledge in the form of future workload prediction to forecast the duration of idle periods. The predicted duration is then used to select an appropriate power state for the idle processor. We proposed five heuristics as part of the DPM and compared their effectiveness using an MPSoC implementation of the H.264 video encoder supporting HD720p at 30 fps. The results show that one of the application prediction based heuristic (MAMAPBH) predicted the most beneficial power states for idle processors with less than 3% error when compared to an optimal solution. In terms of energy savings, MAMAPBH was always within 1% of the energy savings of the optimal solution. When compared with a naive approach (where only one of the possible power states is used for all the idle processors), MAMAPBH achieved up to 40% more energy savings with only 0.5% degradation in throughput. These results signify the importance of leveraging application knowledge at system-level for dynamic power management schemes.