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Integration, the VLSI Journal
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Proceedings of the 48th Design Automation Conference
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia
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Proceedings of the International Conference on Computer-Aided Design
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ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Guarded power gating in a multi-core setting
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A study of the effectiveness of CPU consolidation in a virtualized multi-core server system
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
PGCapping: exploiting power gating for power capping and core lifetime balancing in CMPs
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Virtualizing power distribution in datacenters
Proceedings of the 40th Annual International Symposium on Computer Architecture
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
SMT-centric power-aware thread placement in chip multiprocessors
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
Underprovisioning backup power infrastructure for datacenters
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on Dynamic Voltage and Frequency Scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power management knob for multi-core processors. PCPG is the ability to cut the voltage supply to selected cores, thus reducing to almost zero the leakage power for the gated cores. Using a testbed based on a commercial 4-core chip and a set of real-world application traces from enterprise environments, we have evaluated the potential of PCPG. We show that PCPG can significantly reduce a processor's energy consumption (up to 40%) without significant performance overheads. When compared to DVFS, PCPG is highly effective saving up to 30% more energy than DVFS. When DVFS and PCPG operate together they can save up to almost 60%.