SMT-centric power-aware thread placement in chip multiprocessors

• Authors: Augusto Vega;Alper Buyuktosunoglu;Pradip Bose
• Venue: PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
• Year: 2013

In Simultaneous Multi-Threading (SMT) chip multiprocessors (CMPs), thread placement is performed today in a largely power-unaware manner. For example, consolidation of active threads into fewer cores exposes opportunities for power savings that have not been addressed in prior work. The savings opportunity is especially high in the emerging context where per-core power gating (PCPG) is becoming viable. The use of the optimum combination of core-wise SMT level and number of active cores to achieve a desired power-performance efficiency is a knob which has not been explored in prior work nor implemented as part of the operating system task scheduler. This work investigates the opportunities for such efficiency improvement in the context of the IBM POWER7 processor chip. We present a thread consolidation heuristic (TCH) capable of finding power-performance efficient thread placements at runtime, based on power-performance measurements. In the context of the PARSEC benchmark suite, chip power consumption is reduced by up to 21% (averaged across applications) when TCH is adopted instead of the default Linux thread scheduling policy, with minimal performance impact. TCH can create favorable conditions that enable aggressive actuation of PCPG, when that is available. In conjunction with PCPG, TCH can improve power-performance efficiency by a factor of up to 2.1 with respect to the default scheduler. We also evaluate TCH in the context of the SPECpower benchmark. In this case, TCH reduces system power up to 15% without PCPG and up to 22% with PCPG, with no performance degradation.