SMT-centric power-aware thread placement in chip multiprocessors
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
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Multi-core processors featuring tens or hundreds of cores usually execute on-demand workloads where load balancing is applied to assign threads to cores (like in networking and e-commerce applications). Different load-balancing techniques may result in a distinct power, performance and thermal behavior of the architecture, specially when low-power techniques like power gating are applied to the cores. Power gating each individual core may be too expensive in terms of area (since each core needs to be physically isolated from its neighboring cores using isolation cells and guard bands), and performance (since a core needs to be woken up to execute the next request, incurring a latency penalty). Therefore, processor implementations of a multi-core architecture may choose to group several cores into clusters, where the whole cluster is power gated as opposed to the individual cores. In this work, a load-balancing technique for these clustered multi-core architectures is presented that provides both a low overhead in energy and an a smooth temperature distribution across the die, increasing the reliability of the processor by evenly stressing the cores.