Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Distribution Network Design for VLSI
Power Distribution Network Design for VLSI
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Power gating scheduling for power/ground noise reduction
Proceedings of the 45th annual Design Automation Conference
Effective radii of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Accurate energy breakeven time estimation for run-time power gating
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A robust power gating structure and power mode transition strategy for MTCMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Power Management of Datacenter Workloads Using Per-Core Power Gating
IEEE Computer Architecture Letters
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Power gating has been widely adopted in multicore designs. The design of fast and reliable power mode transition for per-core power gating remains a challenging problem. This paper studies the design methodology for fast power gating wake-up with guaranteed power integrity. Two novel techniques, namely current shaping and multi-thread activation are proposed. Models and physical implementation of both techniques are analyzed. Experimental results demonstrated 1.5 to 11 times wake-up time speedup with no penalty on area or power consumptions by using the proposed techniques.