Genetic and evolutionary algorithms come of age
Communications of the ACM
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Wake-up protocols for controlling current surges in MTCMOS-based technology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power-switch routing for coarse-grain MTCMOS technologies
Proceedings of the 2009 International Conference on Computer-Aided Design
Technique for controlling power-mode transition noise in distributed sleep transistor network
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Comprehensive analysis and control of design parameters for power gated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Towards process variation-aware power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-up sequence control for MTCMOS designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power gating is a technique for efficiently reducing leakage power by disconnecting idle blocks from the power grid. When gated blocks are woken up, large amounts of switching currents are drawn in a short period of time that may introduce severe noise on the power delivery mesh. In this paper, we propose a GA-based approach to schedule power gating considering power/ground noise. We introduce a simulation-based method to accurately and efficiently estimate the worst case noise, taking all the current sources, inductance and decaps' effects into consideration. We also present an incremental scheduling procedure considering the dynamic changes of decap configuration. Experimental results show that by optimally scheduling the wake-up order under time constraints, our technique can reduce noise up to 50% compared to waking gated blocks simultaneously. The quality of results depends upon the total wake-up time constraint, locations of gated blocks, current densities of gated blocks, and decap distribution.