IEEE Transactions on Computers
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A buffer distribution algorithm for high-performance clock net optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On general zero-skew clock net construction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation of cell-based CMOS circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Gate-level current waveform simulation of CMOS integrated circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Min-max linear programming and the timing analysis of digital circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
di/dt Noise in CMOS Integrated Circuits
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Proceedings of the 39th annual Design Automation Conference
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Minimizing peak power in synchronous logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Skew spreading for peak current reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A fast clock scheduling for peak power reduction in LSI
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Power gating scheduling for power/ground noise reduction
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree optimization for electromagnetic compatibility (EMC)
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Peak current reduction by simultaneous state replication and re-encoding
Proceedings of the International Conference on Computer-Aided Design
IR-drop reduction through combinational circuit partitioning
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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