ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
IEEE Transactions on Computers
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimizing Power in ASIC Behavioral Synthesis
IEEE Design & Test
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
High Level Synthesis for Peak Power Minimization Using ILP
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
High-Level Synthesis with Variable-Latency Components
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Energy Efficient Scheduling for Datapath Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Power Supply Noise Suppression via Clock Skew Scheduling
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Datapath Scheduling using Dynamic Frequency Clocking
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A framework for energy and transient power reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast multi-domain clock skew scheduling for peak current reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Skew aware polarity assignment in clock tree
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven high-level synthesis with bit-level chaining and clock selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Peak power reduction has been a critical challenge in the design of integrated circuits impacting the chip's performance and reliability. The reduction of peak power also reduces the power density of integrated circuits. Due to large IR-voltage drops in circuits, transistor switching slows down giving rise to timing violations and logic failures. In this paper, we present a new clock control strategy for peak-power reduction in VLSI circuits. In the proposed method, the simultaneous switching of combinational paths is minimized by taking advantage of the delay slacks among the paths and clustering the paths with similar slack values. Once the paths are identified based on the path delays and their slack values, the clustering algorithm determines the ideal number of clusters for the given circuit and for each cluster the maximum possible phase shift that can be applied to the clock. The paths are assigned to clusters in a load balanced manner based on the slack values and each cluster will have a phase shift possible on its clock depending on the slack. Thus, the proposed register-transfer level (RTL) method takes advantage of the logic-path timing slack to re-schedule circuit activities at optimal intervals within the unaltered clock period. When switching activities are redistributed more evenly across the clock period, the IC supply-current consumption is also spread across a wider range of time within the clock period. This has the beneficial effect of reducing peak-current draw in addition to reducing RMS power draw without having to change the operating frequency and without utilizing additional power supply voltages as in dual or multi VT approaches. The proposed method is implemented and tested through simulations using an experimental setup with Synopsys Tools Suite and Cadence Tools on the ISCAS'85 benchmark circuits, OpenCore circuits and LEON processor multiplier circuit. Experimental results indicate that peak power can be reduced significantly to at least 72% depending on the number of clusters and the phase-shifted clock identified as suitable for the given circuit by the proposed algorithms. Although the proposed method incurs some power overhead compared to the traditional clocking method, the overhead can be made negligible compared to the peak-power reduction as seen in the experimental results presented.