A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Multivoltage scheduling with voltage-partitioned variable storage
Proceedings of the 2003 international symposium on Low power electronics and design
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiple voltage and frequency scheduling for power minimization
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
On multiple-voltage high-level synthesis using algorithmic transformations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WSEAS Transactions on Signal Processing
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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In this paper, we describe a new datapath scheduling algorithm called DFCS based on the concept of dynamic frequency clocking. In dynamic frequency clocking scheme, all functional units in the datapath are driven by a single clock line that switches frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and delays higher frequency operators to later steps. Next, it regroups some of the higher frequency operators with low frequency operators so as to meet the time constraint. During this phase, DFCS assignes the frequency for each cycle and the functional unit with the corresponding voltage. The algorithm has been applied to various high level synthesis benchmark circuits under different time constraints. The experimental results show that using three supply voltage levels (5.0V, 3.3V, 2.4V) and time constraints ({1.5, 1.75 and 2.0} * the critical path delay), average energy savings in the range of 46% to 68% is obtained with respect to using a single-frequency and single-voltage scheme.