Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A multiple clocking scheme for low-power RTL design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
Power: A First Class Design Constraint for Future Architecture and Automation
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
A VLSI array architecture with dynamic frequency clocking
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Compiler-Directed Dynamic Frequency and Voltage Scheduling
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
High Level Synthesis for Peak Power Minimization Using ILP
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Non-Ideal Battery Properties and Low Power Operation in Wearable Computing
ISWC '99 Proceedings of the 3rd IEEE International Symposium on Wearable Computers
Datapath Scheduling using Dynamic Frequency Clocking
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In deep submicron and nanometer designs for batterydriven portable applications, the minimization of total energy,average power, peak power, and peak power differentialare equally important. In this paper, we propose aframework for simultaneous reduction of these energy andtransient power components during behavioral synthesis.A new parameter called "Cycle Power Profile Function"(CPF) is defined which captures the transient power characteristicsas a weighted sum of mean cycle power andmean cycle differential power. Minimizing this parameterusing multiple voltages and dynamic clocking results inreduction of both energy and transient power. Based onthe above, a datapath scheduling algorithm called "CPF-Scheduler"is developed which attempts to minimize theCPF. Experimental results show that for two voltage levels,three operating frequencies, switching activity of 0.5 andpower profiling factor of 0.5, the scheduler achieves (i) totalenergy reductions in the range of 27 - 53%, (ii) averagepower reductions in the range of 40 - 73% (iii) peak powerreductions in the range of 58 - 78% and (iv) peak powerdifferential reductions in the range of 60 - 97%. Further,the impact of switching, profiling factor and resource constraintson the power profile is studied in detail.