Efficient switching activity computation during high-level synthesis of control-dominated designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the 2001 Asia and South Pacific Design Automation Conference
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Proceedings of the 38th annual Design Automation Conference
Bus optimization for low-power data path synthesis based on network flow method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated data path optimization for low power based on network flow method
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A low power scheduler using game theory
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A High-level Interconnect Power Model for Design Space Exploration
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TABS: temperature-aware layout-driven behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel cross-layer optimization of high-level synthesis and physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A game theoretic approach for power optimization during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present SCALP, a comprehensive low-power data path synthesis system that performs the various high-level synthesis tasks (transformations, scheduling, clock selection, module selection, and hardware allocation and assignment) with an aim of reducing the power consumption in the synthesized data path. Focusing on only one or a small subset of the high-level synthesis tasks makes it difficult to realize the full potential for power savings at the algorithm and architecture levels. Our synthesis algorithms, which are based on an iterative improvement strategy with efficient pruning techniques, are capable of performing the various high-level synthesis tasks (and considering their interactions) in an efficient manner. Supply voltage and clock period pruning strategies are used for quickly eliminating inferior design points during the search for the minimum power solution. Estimating switched capacitance accurately at intermediate stages during high-level synthesis can be challenging since the exact structure of the circuit, which affects both physical capacitance and switching activity, may not be available, and due to the high computational complexity of running register-transfer level power analysis tools several times during high-level synthesis. SCALP overcomes the above problems by maintaining a complete image of the structural register-transfer level (RTL) circuit (this is possible since we have a complete solution at any point during iterative improvement), and employing a very fast switched capacitance estimation technique that Is based on the concept of switched capacitance matrices. Our system can handle diverse module libraries and utilize complex scheduling constructs such as multicycling, chaining, and structural pipelining. Retiming and functional pipelining are used in our system to meet tight performance constraints, and to enable the ensuing synthesis steps to better explore the implementation space. Results on several real-life examples are presented to demonstrate the effectiveness of the algorithm. Power estimates obtained using switch-level simulation after layout indicate that up to an order-of-magnitude of power savings can be obtained using our synthesis system