Data structures and network algorithms
Data structures and network algorithms
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory mapping through reducing address bus activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Digital CMOS Design
SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-reliability, low-energy microarchitecture synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early evaluation techniques for low power binding
Proceedings of the 2002 international symposium on Low power electronics and design
An integrated data path optimization for low power based on network flow method
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A High-level Interconnect Power Model for Design Space Exploration
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and RT level of design. This paper addresses the problem of minimizing power dissipated in switching of the buses in data path synthesis. Unlike the previous approaches in which minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on reduction of power dissipated on the buses more fully and effectively. We accomplish this by formulating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds maximum flow of minimum cost solutions in the network. Experimental results on a number of benchmark problems show that given resource and global timing constraints our designs are 22% power-efficient over the designs produced by a random-move based solution, and 18% power-efficient over the designs by a clock-step based optimal solution.